TI compiler

Previous Topic Next Topic
 
classic Classic list List threaded Threaded
38 messages Options
12
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
On 03/06/2017 02:19 PM, Bob von Knobloch wrote:
> Hi David,
> How have you extracted these from the .elf file?

I didn't. You were talking about the .hex file so that is where I looked.

The ISRs start out like this:

__attribute__((wakeup, interrupt(USCI_A1_VECTOR))) void rxISR(void)

--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Announcing the Oxford Dictionaries API! The API offers world-renowned
dictionary content that is easy and intuitive to access. Sign up for an
account today to start using our lexical data to power your apps and
projects. Get started today and enter our developer competition.
http://sdm.link/oxford
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
On 06/03/17 21:53, David W. Schultz wrote:

> On 03/06/2017 02:19 PM, Bob von Knobloch wrote:
>> Hi David,
>> How have you extracted these from the .elf file?
>
> I didn't. You were talking about the .hex file so that is where I looked.
>
> The ISRs start out like this:
>
> __attribute__((wakeup, interrupt(USCI_A1_VECTOR))) void rxISR(void)
>
Thanks David,
I have 2 ISRs in my file. Their .text parts appear in the output, but
the appropriate vector entries are missing.
The compiler does not make a hex file. This is done by objcopy.
Somewhere in your compile command (Makefile?), there is a stanza like
"msp430-elf-objcopy -j text -t data -j vectors -O ihex" or similar.
This places the vectors in the hex file (or, in my case, it doesn't).
If you can find this, I would appreciate a look at it.
Regards,
Bob

--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Announcing the Oxford Dictionaries API! The API offers world-renowned
dictionary content that is easy and intuitive to access. Sign up for an
account today to start using our lexical data to power your apps and
projects. Get started today and enter our developer competition.
http://sdm.link/oxford
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
In reply to this post by David W. Schultz
On 06/03/17 21:53, David W. Schultz wrote:

> On 03/06/2017 02:19 PM, Bob von Knobloch wrote:
>> Hi David,
>> How have you extracted these from the .elf file?
>
> I didn't. You were talking about the .hex file so that is where I looked.
>
> The ISRs start out like this:
>
> __attribute__((wakeup, interrupt(USCI_A1_VECTOR))) void rxISR(void)
>

OK - I have it now,
You put me on the right track David.

I have been used to creating the hex file with "objcopy", in a make
file. For my AVR projects, this copied .text, .data, & .vectors into the
HEX output.

It seems this is unnecessary with msp430-elf-gcc and a simple "objcopy"
from "main.elf" to "main.hex" with no section options does the job, also
including the used ISRs and reset vectors.

Many thanks,
Bob
--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Announcing the Oxford Dictionaries API! The API offers world-renowned
dictionary content that is easy and intuitive to access. Sign up for an
account today to start using our lexical data to power your apps and
projects. Get started today and enter our developer competition.
http://sdm.link/oxford
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
Further work:
having got the compilation under a size which fitted into the flash, I
found that the code did not run. (This is the same source code that
worked fine when compiled with the 'old' mspgcc compiler.)
Inspecting the assembly, I found that the interrupt was suspect.
The 'old' code pushed the registers that it needed, the 'new' TI
compiler pushes (and, of course, later pulls) all of the registers from
r4 - r15 inclusive. This puts a time overhead (a 5 cycles / push & 1MHz
clock) of 90µseconds. My application is processing bits in the interrupt
at 9600 Baud, which is 104.2µsec/bit. Clearly the interrupt overflows in
time.
OK, I would be better off writing the interrupt in assembler, but it
seems quite wasteful to push/pull ALL of the registers (R1, 2 & 3 are
for other purposes).
It seems that the 'old' compiler was very well optimised.
Maybe this helps someone.

Cheers,

Bob
--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
On 03/22/2017 09:54 AM, Bob von Knobloch wrote:
> Inspecting the assembly, I found that the interrupt was suspect.
> The 'old' code pushed the registers that it needed, the 'new' TI
> compiler pushes (and, of course, later pulls) all of the registers from
> r4 - r15 inclusive.

I complained about the failure to follow the EABI (which registers a
called function is required to preserve) to the TI forums some time ago.
(April 2015)

Apparently it still isn't fixed.

Calling another function from the ISR was what triggers this bad
behaviour. Especially if the called function is in another file.

--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
On 22/03/17 16:24, David W. Schultz wrote:
> Calling another function from the ISR was what triggers this bad
> behaviour. Especially if the called function is in another file.
Hi David,
my code doesn't call a function in the interrupt, it merely decrements a
count, tests it for zero and, if not, sets a port bit hi or low, then
exits. This uses only R13 which is why I'm surprised that all the others
are 'push-pulled'. Your description also depicts not the best behaviour.

Bob

--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
On 03/22/2017 10:43 AM, Bob von Knobloch wrote:

> On 22/03/17 16:24, David W. Schultz wrote:
>> Calling another function from the ISR was what triggers this bad
>> behaviour. Especially if the called function is in another file.
> Hi David,
> my code doesn't call a function in the interrupt, it merely decrements a
> count, tests it for zero and, if not, sets a port bit hi or low, then
> exits. This uses only R13 which is why I'm surprised that all the others
> are 'push-pulled'. Your description also depicts not the best behaviour.
>
> Bob
>

I just took a look at some generated code for a simple timer interrupt
and it only saves 5 registers. Just what it used and nothing else.

Compiler version is: msp430-elf-gcc (SOMNIUM Technologies Limited -
msp430-gcc 5.3.0.219) 5.3.0

Not quite the latest.

--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

DJ Delorie
In reply to this post by Bob von Knobloch-2

Could you post your interrupt code (C) and the resulting assembler?
It's hard to debug problems without seeing those...

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
In reply to this post by David W. Schultz
OK,
here is some code that shows the problem.
I use OpenSUSE LEAP 42.1 as the operating system and have both compilers
installed in /opt under 2 different names ("msp430-elf-gcc" for the TI
and "msp-gcc" for the 'old' P.A.Bigot compiler).
Hope it's not too much, I've tried to keep it as small as reasonable
without hiding anything.

The source:
========================================================================================
/*
 
******************************************************************************
 
******************************************************************************
        Compiler test: msp430-elf-gcc
        Includes and Interrupt definition syntax different for 'old' mspgcc
        Otherwise identical
 
******************************************************************************
 
******************************************************************************
  */

#include <msp430.h>
#include <stdint.h>

/*
 
******************************************************************************
  Programmer information *** DO NOT USE IFDEFS *** (AWK'ed by avrprog etc)
  OK to comment out with '//'
 
******************************************************************************
  */

#define    MCU_TARGET msp430g2232

#define    LED BIT0 // LED on P1.0
#define    TXD         BIT1 // TXD on P1.1
#define    RXD BIT2 // RXD on P1.2
#define     Bit_time    104 // 9600 Baud, SMCLK=1MHz (1MHz/9600)=104
#define    Bit_time_5 52 // Time for half a bit.

volatile    uint16_t BitCnt; // Bit count, used when transmitting byte
volatile    uint16_t    TXByte;     // Value sent over UART when
put_char() is called
            uint16_t    result, status, checksum;

/*
 
******************************************************************************
        Write a character to RS232
 
******************************************************************************
  */

static void put_char(uint8_t databyte)
{
     TXByte = databyte;
     TXByte |= 0x100;         // Add stop bit (= 1)
     TXByte <<= 1; // Add start bit (= 0)
     BitCnt = 10;     // Load Bit counter, 8 bits + start + stop

     P1OUT |= TXD;
     TACTL = TASSEL_2 + MC_2;         // SMCLK, continuous mode
     TACCR0 = TAR;         // Initialize compare register
     TACCR0 += Bit_time;         // Set time of first bit
     TACCTL0 =  CCIE; // Enable interrupts
     while (TACCTL0 & CCIE ) {}; // Wait for TX completion (by the
interrupt)
}

/*
 
******************************************************************************
        Main
 
******************************************************************************
  */

void main(void)
{
     WDTCTL = WDTPW | WDTHOLD;     // Stop WDT

     BCSCTL1 = CALBC1_1MHZ;     // Set range
     DCOCTL = CALDCO_1MHZ;     // SMCLK = DCO = 1MHz

     P1DIR |= TXD | LED;

     _NOP();
     _EINT();     // interrupts enabled

     while(1)
     {
        put_char('+');
     }
}
/*
 
******************************************************************************
  Timer A0 interrupt service routine (RS-232 9600 Baud Tx).
  Handles Tx bit timing.
 
******************************************************************************
  */

void __attribute__ ((interrupt (TIMER0_A0_VECTOR))) TIMER0_A0_ISR(void)
{
     P1OUT &= ~LED; // Turn LED on (start of interrupt)
     TACCR0 += Bit_time; // Add Offset to TACCR0
     if (BitCnt == 0) // If all bits TXed
     {
        TACTL = TASSEL_2;         // SMCLK selected, timer off (for power
consumption)
        TACCTL0 &= ~CCIE ;         // Disable interrupt
     }
     else
     {
        if (TXByte & 0x01)
            P1OUT |= TXD;
        else
            P1OUT &= ~TXD;

        TXByte >>= 1;
        BitCnt--;
     }
     P1OUT |= LED; // Turn LED on (end of interrupt)
}
========================================================================================

The compile command for msp430-elf-gcc (taken from running my 'make').

msp430-elf-gcc -I/opt/msp430-gcc/include/ -O2 -Wall -g -mmcu=msp430g2232
  -Wno-main -minrt -fshort-enums -Wno-unused-function   -c -o main.o main.c
msp430-elf-gcc -I/opt/msp430-gcc/include/ -O2 -Wall -g -mmcu=msp430g2232
  -Wno-main -minrt -fshort-enums -Wno-unused-function -Wl,-Map,main.map
-o main.elf main.o
msp430-elf-objdump -h -S main.elf > main.lst

The compile command for 'old' mspgcc (taken from running my
'make').msp430-gcc -Os -Wall -g -mmcu=msp430g2232  -Wno-main
-fshort-enums -Wno-unused-function   -c -o main.o main.c
msp430-gcc -Os -Wall -g -mmcu=msp430g2232  -Wno-main -fshort-enums
-Wno-unused-function -Wl,-Map,main.map -o main.elf main.o
msp430-objdump -h -S main.elf > main.lst
========================================================================================
Listing for msp430-elf-gcc


main.elf:     file format elf32-msp430

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
   0 __interrupt_vector_10 00000002  0000fff2  0000fff2  000002a2  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
   1 __reset_vector 00000002  0000fffe  0000fffe  000002a6  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
   2 .rodata       00000000  0000f800  0000f800  000002a8  2**0
                   CONTENTS, ALLOC, LOAD, DATA
   3 .rodata2      00000000  0000f800  0000f800  000002a8  2**0
                   CONTENTS
   4 .text         000001cc  0000f800  0000f800  000000d4  2**1
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
   5 .data         00000000  00000200  0000f9cc  000002a0  2**0
                   CONTENTS, ALLOC, LOAD, DATA
   6 .bss          0000000a  00000200  0000f9cc  000002a0  2**1
                   ALLOC
   7 .noinit       00000000  0000020a  0000020a  000002a8  2**0
                   CONTENTS
   8 .heap         00000004  0000020a  0000f9cc  000002a2  2**0
                   ALLOC
   9 .MSP430.attributes 00000017  00000000  00000000  000002a8  2**0
                   CONTENTS, READONLY
  10 .comment      00000049  00000000  00000000  000002bf  2**0
                   CONTENTS, READONLY
  11 .debug_aranges 00000020  00000000  00000000  00000308  2**0
                   CONTENTS, READONLY, DEBUGGING
  12 .debug_info   00000c87  00000000  00000000  00000328  2**0
                   CONTENTS, READONLY, DEBUGGING
  13 .debug_abbrev 000001c1  00000000  00000000  00000faf  2**0
                   CONTENTS, READONLY, DEBUGGING
  14 .debug_line   0000026f  00000000  00000000  00001170  2**0
                   CONTENTS, READONLY, DEBUGGING
  15 .debug_frame  000000a0  00000000  00000000  000013e0  2**2
                   CONTENTS, READONLY, DEBUGGING
  16 .debug_str    0000074c  00000000  00000000  00001480  2**0
                   CONTENTS, READONLY, DEBUGGING

Disassembly of section __interrupt_vector_10:

0000fff2 <__interrupt_vector_10>:
     fff2: 8a f8       interrupt service routine at 0xf88a

Disassembly of section .text:

0000f800 <__crt0_start>:
     f800: 31 40 00 03 mov #768, r1 ;#0x0300

0000f804 <__crt0_init_bss>:
     f804: 3c 40 00 02 mov #512, r12 ;#0x0200

0000f808 <.Loc.74.1>:
     f808: 0d 43       clr r13 ;

0000f80a <.Loc.75.1>:
     f80a: 3e 40 0a 00 mov #10, r14 ;#0x000a

0000f80e <.Loc.79.1>:
     f80e: b0 12 b8 f9 call #63928 ;#0xf9b8

0000f812 <__crt0_call_just_main>:
     f812: 0c 43       clr r12 ;

0000f814 <.Loc.181.1>:
     f814: b0 12 18 f8 call #63512 ;#0xf818

0000f818 <main>:
#include "twi.c"
#include "util.c"

void main(void)
{
     WDTCTL = WDTPW | WDTHOLD;     // Stop WDT
     f818: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80
     f81c: 20 01

0000f81e <.Loc.87.1>:

     BCSCTL1 = CALBC1_1MHZ;     // Set range
     f81e: d2 42 ff 10 mov.b &0x10ff,&0x0057 ;0x10ff
     f822: 57 00

0000f824 <.Loc.88.1>:
     DCOCTL = CALDCO_1MHZ;     // SMCLK = DCO = 1MHz
     f824: d2 42 fe 10 mov.b &0x10fe,&0x0056 ;0x10fe
     f828: 56 00

0000f82a <.Loc.90.1>:

     P1DIR |= TXD | LED;
     f82a: f2 d0 03 00 bis.b #3, &0x0022 ;
     f82e: 22 00

0000f830 <.Loc.92.1>:

     _NOP();
     f830: 03 43       nop

0000f832 <.Loc.93.1>:
     _EINT();     // interrupts enabled
     f832: 32 d2       eint
     f834: 03 43       nop

0000f836 <.LBB4>:
 
******************************************************************************
  */

static void put_char(uint8_t databyte)
{
     TXByte = databyte;
     f836: 7b 40 2b 00 mov.b #43, r11 ;#0x002b

0000f83a <.Loc.62.1>:
     TXByte |= 0x100;         // Add stop bit (= 1)
     TXByte <<= 1; // Add start bit (= 0)
     BitCnt = 10;     // Load Bit counter, 8 bits + start + stop
     f83a: 7f 40 0a 00 mov.b #10, r15 ;#0x000a

0000f83e <.Loc.65.1>:

     P1OUT |= TXD;
     TACTL = TASSEL_2 + MC_2;         // SMCLK, continuous mode
     f83e: 3e 40 20 02 mov #544, r14 ;#0x0220

0000f842 <.Loc.68.1>:
     TACCR0 = TAR;         // Initialize compare register
     TACCR0 += Bit_time;         // Set time of first bit
     TACCTL0 =  CCIE; // Enable interrupts
     f842: 7d 40 10 00 mov.b #16, r13 ;#0x0010

0000f846 <.L3>:
 
******************************************************************************
  */

static void put_char(uint8_t databyte)
{
     TXByte = databyte;
     f846: 82 4b 02 02 mov r11, &0x0202 ;

0000f84a <.Loc.60.1>:
     TXByte |= 0x100;         // Add stop bit (= 1)
     f84a: b2 d0 00 01 bis #256, &0x0202 ;#0x0100
     f84e: 02 02

0000f850 <.Loc.61.1>:
     TXByte <<= 1; // Add start bit (= 0)
     f850: 1c 42 02 02 mov &0x0202,r12 ;0x0202
     f854: 0c 5c       rla r12 ;
     f856: 82 4c 02 02 mov r12, &0x0202 ;

0000f85a <.Loc.62.1>:
     BitCnt = 10;     // Load Bit counter, 8 bits + start + stop
     f85a: 82 4f 00 02 mov r15, &0x0200 ;

0000f85e <.Loc.64.1>:

     P1OUT |= TXD;
     f85e: e2 d3 21 00 bis.b #2, &0x0021 ;r3 As==10

0000f862 <.Loc.65.1>:
     TACTL = TASSEL_2 + MC_2;         // SMCLK, continuous mode
     f862: 82 4e 60 01 mov r14, &0x0160 ;

0000f866 <.Loc.66.1>:
     TACCR0 = TAR;         // Initialize compare register
     f866: 92 42 70 01 mov &0x0170,&0x0172 ;0x0170
     f86a: 72 01

0000f86c <.Loc.67.1>:
     TACCR0 += Bit_time;         // Set time of first bit
     f86c: b2 50 68 00 add #104, &0x0172 ;#0x0068
     f870: 72 01

0000f872 <.Loc.68.1>:
     TACCTL0 =  CCIE; // Enable interrupts
     f872: 82 4d 62 01 mov r13, &0x0162 ;

0000f876 <.L2>:
     while (TACCTL0 & CCIE ) {}; // Wait for TX completion (by the
interrupt)
     f876: b2 b0 10 00 bit #16, &0x0162 ;#0x0010
     f87a: 62 01
     f87c: e4 27       jz $-54     ;abs 0xf846
     f87e: b2 b0 10 00 bit #16, &0x0162 ;#0x0010
     f882: 62 01
     f884: f8 23       jnz $-14     ;abs 0xf876
     f886: 30 40 46 f8 br #0xf846 ;

0000f88a <TIMER0_A0_ISR>:
  Handles Tx bit timing.
 
******************************************************************************
  */

void __attribute__ ((interrupt (TIMER0_A0_VECTOR))) TIMER0_A0_ISR(void)
{
     f88a: 0f 12       push r15 ;

0000f88c <.LCFI0>:
     f88c: 0e 12       push r14 ;

0000f88e <.LCFI1>:
     f88e: 0d 12       push r13 ;

0000f890 <.LCFI2>:
     f890: 0c 12       push r12 ;

0000f892 <.LCFI3>:
     f892: 0b 12       push r11 ;

0000f894 <.LCFI4>:
     f894: 0a 12       push r10 ;

0000f896 <.LCFI5>:
     f896: 09 12       push r9 ;

0000f898 <.LCFI6>:
     f898: 08 12       push r8 ;

0000f89a <.LCFI7>:
     f89a: 07 12       push r7 ;

0000f89c <.LCFI8>:
     f89c: 06 12       push r6 ;

0000f89e <.LCFI9>:
     f89e: 05 12       push r5 ;

0000f8a0 <.LCFI10>:
     f8a0: 04 12       push r4 ;

0000f8a2 <.LCFI11>:
     P1OUT &= ~LED; // Turn LED on (start of interrupt)
     f8a2: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01

0000f8a6 <.Loc.118.1>:
     TACCR0 += Bit_time; // Add Offset to TACCR0
     f8a6: b2 50 68 00 add #104, &0x0172 ;#0x0068
     f8aa: 72 01

0000f8ac <.Loc.119.1>:
     if (BitCnt == 0) // If all bits TXed
     f8ac: 1c 42 00 02 mov &0x0200,r12 ;0x0200
     f8b0: 0c 93       cmp #0, r12 ;r3 As==00
     f8b2: 20 24       jz $+66     ;abs 0xf8f4

0000f8b4 <.Loc.126.1>:
        TACTL = TASSEL_2;         // SMCLK selected, timer off (for power
consumption)
        TACCTL0 &= ~CCIE ;         // Disable interrupt
     }
     else
     {
        if (TXByte & 0x01)
     f8b4: 92 b3 02 02 bit #1, &0x0202 ;r3 As==01
     f8b8: 19 20       jnz $+52     ;abs 0xf8ec

0000f8ba <.Loc.129.1>:
            P1OUT |= TXD;
        else
            P1OUT &= ~TXD;
     f8ba: e2 c3 21 00 bic.b #2, &0x0021 ;r3 As==10

0000f8be <.L11>:

        TXByte >>= 1;
     f8be: 1c 42 02 02 mov &0x0202,r12 ;0x0202
     f8c2: b0 12 3c f9 call #63804 ;#0xf93c
     f8c6: 82 4c 02 02 mov r12, &0x0202 ;

0000f8ca <.Loc.132.1>:
        BitCnt--;
     f8ca: b2 53 00 02 add #-1, &0x0200 ;r3 As==11

0000f8ce <.L9>:
     }
     P1OUT |= LED; // Turn LED on (end of interrupt)
     f8ce: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01

0000f8d2 <.Loc.135.1>:
}
     f8d2: 34 41       pop r4 ;
     f8d4: 35 41       pop r5 ;
     f8d6: 36 41       pop r6 ;
     f8d8: 37 41       pop r7 ;
     f8da: 38 41       pop r8 ;
     f8dc: 39 41       pop r9 ;
     f8de: 3a 41       pop r10 ;
     f8e0: 3b 41       pop r11 ;
     f8e2: 3c 41       pop r12 ;
     f8e4: 3d 41       pop r13 ;
     f8e6: 3e 41       pop r14 ;
     f8e8: 3f 41       pop r15 ;
     f8ea: 00 13       reti

0000f8ec <.L13>:
        TACCTL0 &= ~CCIE ;         // Disable interrupt
     }
     else
     {
        if (TXByte & 0x01)
            P1OUT |= TXD;
     f8ec: e2 d3 21 00 bis.b #2, &0x0021 ;r3 As==10
     f8f0: 30 40 be f8 br #0xf8be ;

0000f8f4 <.L12>:
{
     P1OUT &= ~LED; // Turn LED on (start of interrupt)
     TACCR0 += Bit_time; // Add Offset to TACCR0
     if (BitCnt == 0) // If all bits TXed
     {
        TACTL = TASSEL_2;         // SMCLK selected, timer off (for power
consumption)
     f8f4: b2 40 00 02 mov #512, &0x0160 ;#0x0200
     f8f8: 60 01

0000f8fa <.Loc.122.1>:
        TACCTL0 &= ~CCIE ;         // Disable interrupt
     f8fa: b2 f0 ef ff and #65519, &0x0162 ;#0xffef
     f8fe: 62 01
     f900: 30 40 ce f8 br #0xf8ce ;

0000f904 <__mspabi_srli_15>:
     f904: 12 c3       clrc
     f906: 0c 10       rrc r12 ;

0000f908 <__mspabi_srli_14>:
     f908: 12 c3       clrc
     f90a: 0c 10       rrc r12 ;

0000f90c <__mspabi_srli_13>:
     f90c: 12 c3       clrc
     f90e: 0c 10       rrc r12 ;

0000f910 <__mspabi_srli_12>:
     f910: 12 c3       clrc
     f912: 0c 10       rrc r12 ;

0000f914 <__mspabi_srli_11>:
     f914: 12 c3       clrc
     f916: 0c 10       rrc r12 ;

0000f918 <__mspabi_srli_10>:
     f918: 12 c3       clrc
     f91a: 0c 10       rrc r12 ;

0000f91c <__mspabi_srli_9>:
     f91c: 12 c3       clrc
     f91e: 0c 10       rrc r12 ;

0000f920 <__mspabi_srli_8>:
     f920: 12 c3       clrc
     f922: 0c 10       rrc r12 ;

0000f924 <__mspabi_srli_7>:
     f924: 12 c3       clrc
     f926: 0c 10       rrc r12 ;

0000f928 <__mspabi_srli_6>:
     f928: 12 c3       clrc
     f92a: 0c 10       rrc r12 ;

0000f92c <__mspabi_srli_5>:
     f92c: 12 c3       clrc
     f92e: 0c 10       rrc r12 ;

0000f930 <__mspabi_srli_4>:
     f930: 12 c3       clrc
     f932: 0c 10       rrc r12 ;

0000f934 <__mspabi_srli_3>:
     f934: 12 c3       clrc
     f936: 0c 10       rrc r12 ;

0000f938 <__mspabi_srli_2>:
     f938: 12 c3       clrc
     f93a: 0c 10       rrc r12 ;

0000f93c <__mspabi_srli_1>:
     f93c: 12 c3       clrc
     f93e: 0c 10       rrc r12 ;
     f940: 30 41       ret

0000f942 <.L11>:
     f942: 3d 53       add #-1, r13 ;r3 As==11
     f944: 12 c3       clrc
     f946: 0c 10       rrc r12 ;

0000f948 <__mspabi_srli>:
     f948: 0d 93       cmp #0, r13 ;r3 As==00
     f94a: fb 23       jnz $-8       ;abs 0xf942
     f94c: 30 41       ret

0000f94e <__mspabi_srll_15>:
     f94e: 12 c3       clrc
     f950: 0d 10       rrc r13 ;
     f952: 0c 10       rrc r12 ;

0000f954 <__mspabi_srll_14>:
     f954: 12 c3       clrc
     f956: 0d 10       rrc r13 ;
     f958: 0c 10       rrc r12 ;

0000f95a <__mspabi_srll_13>:
     f95a: 12 c3       clrc
     f95c: 0d 10       rrc r13 ;
     f95e: 0c 10       rrc r12 ;

0000f960 <__mspabi_srll_12>:
     f960: 12 c3       clrc
     f962: 0d 10       rrc r13 ;
     f964: 0c 10       rrc r12 ;

0000f966 <__mspabi_srll_11>:
     f966: 12 c3       clrc
     f968: 0d 10       rrc r13 ;
     f96a: 0c 10       rrc r12 ;

0000f96c <__mspabi_srll_10>:
     f96c: 12 c3       clrc
     f96e: 0d 10       rrc r13 ;
     f970: 0c 10       rrc r12 ;

0000f972 <__mspabi_srll_9>:
     f972: 12 c3       clrc
     f974: 0d 10       rrc r13 ;
     f976: 0c 10       rrc r12 ;

0000f978 <__mspabi_srll_8>:
     f978: 12 c3       clrc
     f97a: 0d 10       rrc r13 ;
     f97c: 0c 10       rrc r12 ;

0000f97e <__mspabi_srll_7>:
     f97e: 12 c3       clrc
     f980: 0d 10       rrc r13 ;
     f982: 0c 10       rrc r12 ;

0000f984 <__mspabi_srll_6>:
     f984: 12 c3       clrc
     f986: 0d 10       rrc r13 ;
     f988: 0c 10       rrc r12 ;

0000f98a <__mspabi_srll_5>:
     f98a: 12 c3       clrc
     f98c: 0d 10       rrc r13 ;
     f98e: 0c 10       rrc r12 ;

0000f990 <__mspabi_srll_4>:
     f990: 12 c3       clrc
     f992: 0d 10       rrc r13 ;
     f994: 0c 10       rrc r12 ;

0000f996 <__mspabi_srll_3>:
     f996: 12 c3       clrc
     f998: 0d 10       rrc r13 ;
     f99a: 0c 10       rrc r12 ;

0000f99c <__mspabi_srll_2>:
     f99c: 12 c3       clrc
     f99e: 0d 10       rrc r13 ;
     f9a0: 0c 10       rrc r12 ;

0000f9a2 <__mspabi_srll_1>:
     f9a2: 12 c3       clrc
     f9a4: 0d 10       rrc r13 ;
     f9a6: 0c 10       rrc r12 ;
     f9a8: 30 41       ret

0000f9aa <.L12>:
     f9aa: 3e 53       add #-1, r14 ;r3 As==11
     f9ac: 12 c3       clrc
     f9ae: 0d 10       rrc r13 ;
     f9b0: 0c 10       rrc r12 ;

0000f9b2 <__mspabi_srll>:
     f9b2: 0e 93       cmp #0, r14 ;r3 As==00
     f9b4: fa 23       jnz $-10     ;abs 0xf9aa
     f9b6: 30 41       ret

0000f9b8 <memset>:
     f9b8: 0f 4c       mov r12, r15 ;
     f9ba: 0e 5c       add r12, r14 ;

0000f9bc <.L2>:
     f9bc: 0f 9e       cmp r14, r15 ;
     f9be: 01 20       jnz $+4       ;abs 0xf9c2

0000f9c0 <.Loc.104.1>:
     f9c0: 30 41       ret

0000f9c2 <.L3>:
     f9c2: cf 4d 00 00 mov.b r13, 0(r15) ;
     f9c6: 1f 53       inc r15 ;

0000f9c8 <.LVL4>:
     f9c8: 30 40 bc f9 br #0xf9bc ;

========================================================================================
Listing for 'old' mspgcc.


main.elf:     file format elf32-msp430

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
   0 .text         000000fa  0000f800  0000f800  000000b4  2**1
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
   1 .bss          0000000a  00000200  0000f8fa  000001ae  2**1
                   ALLOC
   2 .noinit       00000002  0000020a  0000f8fa  000001ae  2**1
                   ALLOC
   3 .vectors      00000020  0000ffe0  0000ffe0  000001ae  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
   4 .comment      00000030  00000000  00000000  000001ce  2**0
                   CONTENTS, READONLY
   5 .debug_aranges 000000a4  00000000  00000000  00000200  2**2
                   CONTENTS, READONLY, DEBUGGING
   6 .debug_info   000005d2  00000000  00000000  000002a4  2**0
                   CONTENTS, READONLY, DEBUGGING
   7 .debug_abbrev 00000169  00000000  00000000  00000876  2**0
                   CONTENTS, READONLY, DEBUGGING
   8 .debug_line   00000340  00000000  00000000  000009df  2**0
                   CONTENTS, READONLY, DEBUGGING
   9 .debug_frame  00000030  00000000  00000000  00000d20  2**1
                   CONTENTS, READONLY, DEBUGGING
  10 .debug_str    000001a1  00000000  00000000  00000d50  2**0
                   CONTENTS, READONLY, DEBUGGING
  11 .debug_loc    00000014  00000000  00000000  00000ef1  2**0
                   CONTENTS, READONLY, DEBUGGING
  12 .debug_ranges 0000000c  00000000  00000000  00000f05  2**0
                   CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

0000f800 <__watchdog_support>:
     f800: 55 42 20 01 mov.b &0x0120,r5
     f804: 35 d0 08 5a bis #23048, r5 ;#0x5a08
     f808: 82 45 0a 02 mov r5, &0x020a

0000f80c <__init_stack>:
     f80c: 31 40 00 03 mov #768, r1 ;#0x0300

0000f810 <__do_copy_data>:
     f810: 3f 40 00 00 mov #0, r15 ;#0x0000
     f814: 0f 93       tst r15
     f816: 08 24       jz $+18     ;abs 0xf828
     f818: 92 42 0a 02 mov &0x020a,&0x0120
     f81c: 20 01
     f81e: 2f 83       decd r15
     f820: 9f 4f fa f8 mov -1798(r15),512(r15);0xf8fa(r15), 0x0200(r15)
     f824: 00 02
     f826: f8 23       jnz $-14     ;abs 0xf818

0000f828 <__do_clear_bss>:
     f828: 3f 40 0a 00 mov #10, r15 ;#0x000a
     f82c: 0f 93       tst r15
     f82e: 07 24       jz $+16     ;abs 0xf83e
     f830: 92 42 0a 02 mov &0x020a,&0x0120
     f834: 20 01
     f836: 1f 83       dec r15
     f838: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15)
     f83c: f9 23       jnz $-12     ;abs 0xf830

0000f83e <main>:
#include "twi.c"
#include "util.c"

void main(void)
{
     WDTCTL = WDTPW | WDTHOLD;     // Stop WDT
     f83e: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80
     f842: 20 01

     BCSCTL1 = CALBC1_1MHZ;     // Set range
     f844: d2 42 ff 10 mov.b &0x10ff,&0x0057
     f848: 57 00
     DCOCTL = CALDCO_1MHZ;     // SMCLK = DCO = 1MHz
     f84a: d2 42 fe 10 mov.b &0x10fe,&0x0056
     f84e: 56 00

     P1DIR |= TXD | LED;
     f850: f2 d0 03 00 bis.b #3, &0x0022 ;#0x0003
     f854: 22 00

     _NOP();
     f856: 03 43       nop
     _EINT();     // interrupts enabled
     f858: 32 d2       eint
 
******************************************************************************
  */

static void put_char(uint8_t databyte)
{
     TXByte = databyte;
     f85a: b2 40 2b 00 mov #43, &0x0202 ;#0x002b
     f85e: 02 02
     TXByte |= 0x100;         // Add stop bit (= 1)
     f860: b2 d0 00 01 bis #256, &0x0202 ;#0x0100
     f864: 02 02
     TXByte <<= 1; // Add start bit (= 0)
     f866: 1f 42 02 02 mov &0x0202,r15
     f86a: 0f 5f       rla r15
     f86c: 82 4f 02 02 mov r15, &0x0202
     BitCnt = 10;     // Load Bit counter, 8 bits + start + stop
     f870: b2 40 0a 00 mov #10, &0x0200 ;#0x000a
     f874: 00 02

     P1OUT |= TXD;
     f876: e2 d3 21 00 bis.b #2, &0x0021 ;r3 As==10
     TACTL = TASSEL_2 + MC_2;         // SMCLK, continuous mode
     f87a: b2 40 20 02 mov #544, &0x0160 ;#0x0220
     f87e: 60 01
     TACCR0 = TAR;         // Initialize compare register
     f880: 92 42 70 01 mov &0x0170,&0x0172
     f884: 72 01
     TACCR0 += Bit_time;         // Set time of first bit
     f886: b2 50 68 00 add #104, &0x0172 ;#0x0068
     f88a: 72 01
     TACCTL0 =  CCIE; // Enable interrupts
     f88c: b2 40 10 00 mov #16, &0x0162 ;#0x0010
     f890: 62 01
     while (TACCTL0 & CCIE ) {}; // Wait for TX completion (by the
interrupt)
     f892: b2 b0 10 00 bit #16, &0x0162 ;#0x0010
     f896: 62 01
     f898: fc 23       jnz $-6       ;abs 0xf892
     f89a: df 3f       jmp $-64     ;abs 0xf85a

0000f89c <__stop_progExec__>:
     f89c: 32 d0 f0 00 bis #240, r2 ;#0x00f0
     f8a0: fd 3f       jmp $-4       ;abs 0xf89c

0000f8a2 <__ctors_end>:
     f8a2: 30 40 f8 f8 br #0xf8f8

0000f8a6 <TIMER0_A0_ISR>:
  Handles Tx bit timing.
 
******************************************************************************
  */

interrupt (TIMER0_A0_VECTOR) TIMER0_A0_ISR(void)
{
     f8a6: 0f 12       push r15
     P1OUT &= ~LED; // Turn LED on (start of interrupt)
     f8a8: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01
     TACCR0 += Bit_time; // Add Offset to TACCR0
     f8ac: b2 50 68 00 add #104, &0x0172 ;#0x0068
     f8b0: 72 01
     if (BitCnt == 0) // If all bits TXed
     f8b2: 1f 42 00 02 mov &0x0200,r15
     f8b6: 0f 93       tst r15
     f8b8: 07 20       jnz $+16     ;abs 0xf8c8
     {
        TACTL = TASSEL_2;         // SMCLK selected, timer off (for power
consumption)
     f8ba: b2 40 00 02 mov #512, &0x0160 ;#0x0200
     f8be: 60 01
        TACCTL0 &= ~CCIE ;         // Disable interrupt
     f8c0: b2 f0 ef ff and #-17, &0x0162 ;#0xffef
     f8c4: 62 01
     f8c6: 14 3c       jmp $+42     ;abs 0xf8f0
     }
     else
     {
        if (TXByte & 0x01)
     f8c8: 92 b3 02 02 bit #1, &0x0202 ;r3 As==01
     f8cc: 04 24       jz $+10     ;abs 0xf8d6
            P1OUT |= TXD;
     f8ce: 5f 42 21 00 mov.b &0x0021,r15
     f8d2: 6f d3       bis.b #2, r15 ;r3 As==10
     f8d4: 03 3c       jmp $+8       ;abs 0xf8dc
        else
            P1OUT &= ~TXD;
     f8d6: 5f 42 21 00 mov.b &0x0021,r15
     f8da: 6f c3       bic.b #2, r15 ;r3 As==10
     f8dc: c2 4f 21 00 mov.b r15, &0x0021

        TXByte >>= 1;
     f8e0: 1f 42 02 02 mov &0x0202,r15
     f8e4: 12 c3       clrc
     f8e6: 0f 10       rrc r15
     f8e8: 82 4f 02 02 mov r15, &0x0202
        BitCnt--;
     f8ec: b2 53 00 02 add #-1, &0x0200 ;r3 As==11
     }
     P1OUT |= LED; // Turn LED on (end of interrupt)
     f8f0: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01
}
     f8f4: 3f 41       pop r15
     f8f6: 00 13       reti

0000f8f8 <_unexpected_>:
     f8f8: 00 13       reti

Disassembly of section .vectors:

0000ffe0 <__ivtbl_16>:
     ffe0: a2 f8 a2 f8 a2 f8 a2 f8 a2 f8 a2 f8 a2 f8 a2 f8
................
     fff0: a2 f8 a6 f8 a2 f8 a2 f8 a2 f8 a2 f8 a2 f8 00 f8
................



------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
While you didn't explicitly call a function in your interrupt routine,
the compiler did for the right shift of TXByte.

Making TXByte a signed int makes this go away. (The MSP430 doesn't have
a single instruction to do the unsigned right shift.) You don't need for
it to be unsigned because you don't care about those bits.



A minor nit:

Making TXByte and BitCnt volatile buys you nothing except slower code.

Their values can't change while the interrupt is being serviced so it
doesn't help there. They also can't change while you aren't looking in
put_char() because it waits for the timer to finish.

--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
On 23/03/17 11:45, David W. Schultz wrote:
> While you didn't explicitly call a function in your interrupt routine,
> the compiler did for the right shift of TXByte.

Which the 'old' compiler doesn't.

And your complaint to TI of April 2015 appears to have been ignored.

> Making TXByte a signed int makes this go away. (The MSP430 doesn't have
> a single instruction to do the unsigned right shift.) You don't need for
> it to be unsigned because you don't care about those bits.

In this case, true, but irritating.

> A minor nit:
>
> Making TXByte and BitCnt volatile buys you nothing except slower code.

Yes, I forgot to remove this. It was just an attempt to try to influence
the compiler.

Is there any way of inputting this to TI?

and

Do you know where there is proper documentation of their instruction
set? What I have from TI is scant, to say the least.

Thanks,

Bob


------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
On 03/23/2017 06:13 AM, Bob von Knobloch wrote:
> Do you know where there is proper documentation of their instruction
> set? What I have from TI is scant, to say the least.

The family guides have complete descriptions. In this case slau144.


--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
On 23/03/17 15:10, David W. Schultz wrote:
> The family guides have complete descriptions. In this case slau144.

Thanks David, I seem to have missed that, it is indeed a proper description.
Thanks for all the help. The TI compiler is still no good - the
interrupts are still taking much longer that the old compiler and the
code size is still much bigger.
The enhancements that I wanted to do to the target can, seemingly, only
be achieved with the old compiler at this time.
I'll give up on the TI one and keep looking in case it improves.

Cheers,

Bob

--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Grant Edwards-6
On 2017-03-24, Bob von Knobloch <[hidden email]> wrote:
> On 23/03/17 15:10, David W. Schultz wrote:
>> The family guides have complete descriptions. In this case slau144.
>
> Thanks David, I seem to have missed that, it is indeed a proper description.
> Thanks for all the help. The TI compiler is still no good - the
> interrupts are still taking much longer that the old compiler and the
> code size is still much bigger.

After seeing the mess they made of Code Composter, I can't say I'm
surprised they've mulched the gcc port.

> The enhancements that I wanted to do to the target can, seemingly, only
> be achieved with the old compiler at this time.
>
> I'll give up on the TI one and keep looking in case it improves.

I predict it will get worse and worse until it gets forked and
somebody else fixes it.

--
Grant Edwards               grant.b.edwards        Yow! Is my fallout shelter
                                  at               termite proof?
                              gmail.com            


------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Przemek Klosowski-2
On Fri, Mar 24, 2017 at 10:43 AM, Grant Edwards
<[hidden email]> wrote:

> I predict it will get worse and worse until it gets forked and
> somebody else fixes it.
I thought someone suggested that the interrupt routine saves too many
registers because it ends up calling a runtime function because one of
the variables has a wrong type (or rather, type that is not optimal
for this case).

Bob, did you check whether changing the declared type avoids calling
the runtime, and avoids excessive register saving/restoring?

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

Bob von Knobloch-2
On 24/03/17 19:00, Przemek Klosowski wrote:
> Bob, did you check whether changing the declared type avoids calling
> the runtime, and avoids excessive register saving/restoring?

Yes Przemek,
David Schultz kindly informed me that a right shift, as it is not
natively supported, can cause this. Changing to a int16_t cured this,
suppressing the unwanted push/pull pairs.
However, the binary is still far bigger and slower than the 'old' mspgcc
compiler, so I'm sticking with that for now.
Cheers,
Bob

--
The Sun is out, the sky is blue, it's time to drive the MR2.

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

William "Chops" Westfield
In reply to this post by David W. Schultz
On Mar 23, 2017, at 3:45 AM, David W. Schultz <[hidden email]> wrote:

> Making TXByte a signed int makes this go away. (The MSP430 doesn't have
> a single instruction to do the unsigned right shift.) You don't need for
> it to be unsigned because you don't care about those bits.

Why does it need to be a “single instruction” for the compiler to create inline code for the shift
(two instruction: "clrc; rrc", right) instead of pulling in (apparently) a library that includes code for every possible shift count and size?

Also: https://www.securecoding.cert.org/confluence/display/c/INT13-C.+Use+bitwise+operators+only+on+unsigned+operands

BillW


------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
Reply | Threaded
Open this post in threaded view
|

Re: TI compiler

David W. Schultz
On 03/24/2017 05:39 PM, William Westfield wrote:
> Why does it need to be a “single instruction” for the compiler to
> create inline code for the shift (two instruction: "clrc; rrc",
> right) instead of pulling in (apparently) a library that includes
> code for every possible shift count and size?
>

It doesn't have to be, it is just a hint at what happened.

I did notice that the compiler produced the clrc; rrc pair when shifting
a device register value on a FR5969. I had expected the rrux
instruction (with optional repeat count) but the code size is the same.
At least for single shifts.


Oh, another thing to try to reduce the final code size is to pass the
option "--gc-sections" to the linker. This enables garbage collection on
unused code. I just enabled it on a FR5969 project and it reduced the
code size from 23071 bytes to 19812.

--
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." - Anthony Bourdain

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Mspgcc-users mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/mspgcc-users
12