MSP430 instruction pipeline

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MSP430 instruction pipeline

Jose Luis Honorato L.
Hi,

An e-mail from Peter a few days ago hinted the existence of an instruction
pipeline in msp430. It is barely mentioned in the docs and Google results
only seem to mention the lack of information about it.

I'd like to read more, does anyone know where to look?

Thanks in advance,
Jose

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Re: MSP430 instruction pipeline

Eric Decker
I haven't seen any thing that describes the internal architecture of the
MSP430.   And I've looked.

Sorry.


On Mon, Jun 16, 2014 at 8:36 PM, Jose Luis Honorato L. <
[hidden email]> wrote:

> Hi,
>
> An e-mail from Peter a few days ago hinted the existence of an instruction
> pipeline in msp430. It is barely mentioned in the docs and Google results
> only seem to mention the lack of information about it.
>
> I'd like to read more, does anyone know where to look?
>
> Thanks in advance,
> Jose
>
>
> ------------------------------------------------------------------------------
> HPCC Systems Open Source Big Data Platform from LexisNexis Risk Solutions
> Find What Matters Most in Your Big Data with HPCC Systems
> Open Source. Fast. Scalable. Simple. Ideal for Dirty Data.
> Leverages Graph Analysis for Fast Processing & Easy Data Exploration
> http://p.sf.net/sfu/hpccsystems
> _______________________________________________
> Mspgcc-users mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/mspgcc-users
>
>

--
Eric B. Decker
Senior (over 50 :-) Researcher

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Re: MSP430 instruction pipeline

Peter Bigot-4
In reply to this post by Jose Luis Honorato L.
On the whole I agree with Eric that there is little public information
about the internal CPU architecture.  If you still want to dig around,
the three data sources I'd recommend are:

* the CPU sections of the various family users guides, in particular
the instruction timing tables.  Differences among the instructions
based on source and destination alternatives, as well as the same
instruction on CPU and CPUX, suggest pipeline differences.

* various postings on
http://e2e.ti.com/support/microcontrollers/msp430/default.aspx, though
realize that most will be speculation.

* experimentation to time the duration of different sequences.
https://github.com/pabigot/bsp430/blob/master/examples/platform/cpu42/main.c
 uses a low-speed clock technique that tests whether erratum CPU42
(the CPUX bug about EINT without NOP) is present on a particular
device.  Adapt that to use a clock source synchronized with MCLK
instead, and put the reads around the sequence to be timed instead of
adjacent.

Peter

On Mon, Jun 16, 2014 at 10:36 PM, Jose Luis Honorato L.
<[hidden email]> wrote:

> Hi,
>
> An e-mail from Peter a few days ago hinted the existence of an instruction
> pipeline in msp430. It is barely mentioned in the docs and Google results
> only seem to mention the lack of information about it.
>
> I'd like to read more, does anyone know where to look?
>
> Thanks in advance,
> Jose
>
> ------------------------------------------------------------------------------
> HPCC Systems Open Source Big Data Platform from LexisNexis Risk Solutions
> Find What Matters Most in Your Big Data with HPCC Systems
> Open Source. Fast. Scalable. Simple. Ideal for Dirty Data.
> Leverages Graph Analysis for Fast Processing & Easy Data Exploration
> http://p.sf.net/sfu/hpccsystems
> _______________________________________________
> Mspgcc-users mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/mspgcc-users
>

------------------------------------------------------------------------------
HPCC Systems Open Source Big Data Platform from LexisNexis Risk Solutions
Find What Matters Most in Your Big Data with HPCC Systems
Open Source. Fast. Scalable. Simple. Ideal for Dirty Data.
Leverages Graph Analysis for Fast Processing & Easy Data Exploration
http://p.sf.net/sfu/hpccsystems
_______________________________________________
Mspgcc-users mailing list
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